This invention relates to a television receiver capable of simultaneously displaying color pictures of two channels on a single screen thereof.
Japanese Patent Application Kokai (Laid-Open) No. 49-2419 discloses a method of simultaneously displaying pictures of two channels A and B on the same screen of a television receiver. For a better understanding of the present invention, the disclosure of the cited patent application will be described with reference to FIGS. 1 and 2 before describing the present invention in detail.
Referring to FIG. 1, the picture of the channel B occupies approximately the quarter of the total area of the screen with a height and a width which are approximately the half of those of the screen, and is displayed on the lower right corner portion of the screen. According to the basic principle of the method disclosed in the cited patent application, alternate ones of picture elements (sampling points required for picture reproduction) in alternate scanning periods for the channel B are sampled to be stored in a memory circuit, and during scanning on the screen portion B in FIG. 1 by the horizontal scanning lines for the channel A, the sampled values stored in the memory circuit are read out at a rate two times the rate of writing so that the picture of the channel B can be displayed on the screen portion B in FIG. 1 in a relation in which it is compressed approximately to the half in both the height and the width.
FIG. 2 shows the practical structure of the system employed in the aforesaid patent application. The system comprises an antenna 1, tuners 2 and 6 receiving two color television signals of different channels A and B respectively, video intermediate frequency amplifiers 3 and 7, video detectors 4 and 8, video amplifiers 5 and 9, a synchronizing signal separator 10 separating the vertical synchronizing signal V.sub.B and horizontal synchronizing signal H.sub.B of the channel B from the output of the video amplifier 9, and another synchronizing signal separator 11 separating the vertical synchronizing signal V.sub.A and horizontal synchronizing signal H.sub.B of the channel A from the output of the video amplifier 5. A flip-flop 12 is inverted in its state in response to the application of the horizontal synchronizing signal H.sub.B, and an output signal d appears from the flip-flop 12. An input p representing the video signal of the channel A is directly applied from the video amplifier 5 to a signal selecting circuit 13 together with inputs q, r and s applied from a memory circuit (not shown) which stores alternately the video signal portions of the channel B. Selection control signals N.sub.0, N.sub.1, N.sub.2 and N.sub.3 are applied to the signal selecting circuit 13 from a control circuitry 20, and this circuit 13 selects one of the input signals p, q, r and s, so that a corresponding output signal appears at its output terminal 23. RS flip-flops 14 and 17 each having a reset terminal R and a set terminal S generate an output a and an output b respectively. Counters 15 and 16 are connected at their output terminals to the set terminals of the RS flip-flops 14 and 17 respectively. A gated oscillator 18 is reset or ceases to oscillate each time the horizontal synchronizing signal H.sub.A appears from the synchronizing signal separator 11 so that the phase of the first pulse of its output pulse signal relative to the horizontal synchronizing signal H.sub.A can be maintained constant during each horizontal scanning period. Another gated oscillator 19 generating an output pulse signal f has a similar relationship with respect to the horizontal synchronizing signal H.sub.B. The control circuitry 20 includes the memory circuit consisting of three analog memories of CCD or BBD structure and storing picture information written therein to be read out therefrom. The outputs a and b of the respective RS flip-flops 14 and 17 are connected to an AND gate 21 which generates an output c applied to another AND gate 22 together with the output of the gated oscillator 18.
The oscillation frequency of the first gated oscillator 18 is 450 f.sub.H [Hz] when the number of picture elements in one horizontal scanning period is 450 and the horizontal scanning frequency is f.sub.H. The oscillation frequency of the second gated oscillator 19 is 225 f.sub.H [Hz] which is the half of that of the first gated oscillator 18. The first counter 15 has a capacity for counting 525/2.times.2.revreaction.132 bits where 525/2 is the number of horizontal scanning lines for one field. Thus, this counter 15 sets the RS flip-flop 14 when it has counted 132 pulses of the horizontal synchronizing signal H.sub.A, and an output a of high level appears from the flip-flop 14. This first counter 15 and the flip-flop 14 are reset by the vertical synchronizing signal V.sub.A. The second counter 16 has a capacity for counting 450/2=225 bits where 450 is the number of picture elements in one horizontal scanning period. This counter 16 sets the RS flip-flop 17 when it has counted 225 output pulses of the first gated oscillator 18, and an output b of high level appears from the flip-flop 17. The second counter 16 and the flip-flop 17 are reset by the horizontal synchronizing signal H.sub.A. Thus, during scanning on the screen portion B shown in FIG. 1, the outputs a and b of high level appear from the respective flip-flops 14 and 17, and the output of the first gated oscillator 18 appears as an output e of the AND gate 22.
In the system having the structure shown in FIG. 2, a transmitted television signal of the channel A as shown in FIG. 3A is selected by the tuner 2 and is then passed through the video intermediate frequency amplifier 3, video detector 4 and video amplifier 5 to be applied to the signal selecting circuit 13 as a video signal p. Another transmitted television signal of the channel B is selected by the tuner 6 and is then passed through the video intermediate frequency amplifier 7, video detector 8 and video amplifier 9 to be applied to the control circuit 20 as a video signal v. The control circuitry 20 includes three analog memories of CCD or BBD structure and control circuit for alternately actuating these memories. In this control circuitry 20, the video signal v of the channel B is sampled in a manner as shown in FIG. 3B, and the sampled signal portions of successive fields are stored in different ones of these analog memories respectively. After the analog memories have completed the writing, the stored signal portions are successively read out at a rate two times the rate of sampling, so that a video signal as shown in FIG. 3C is obtained in which the time axis is compressed to the half of the original time axis. Video signals q, r and s appear for the successive fields respectively. The video signals p, q, r and s are suitably selected by the signal selecting circuit 13 so that a video signal waveform as shown in FIG. 3D appears at the output terminal 23 of the signal selecting circuit 13. It will be seen from FIG. 3D that the video signal of the channel A and the video signal of the channel B are combined in the output of the circuit 13 to display the pictures of the two channels in accordance with the display pattern shown in FIG. 1.